When different circuits are coupled to each other, often the impedances thereof do not match. Therefore, an impedance matching network may be required to match the output impedance of a first unit to the input impedance of a second subsequent unit, i.e. the output impedance of a source is made equal to the output impedance of a load. Here, the first impedance can be e.g. an amplifier stage in a RF circuit and the second impedance may be an input impedance of an amplifier stage or an antenna.
WO 2004/055839 A1 discloses a planar inductive component which is arranged over a substrate. The substrate comprises a winding which is situated in a first plane and a patent ground shield for shielding the winding from the substrate.
FIGS. 1A and 1B show a circuit diagram of Pi matching networks according to the prior art. The matching network according to FIG. 1A comprises an inductor L, two capacitors C, connecting a load with an input impedance Z1 to a source with an output impedance. It should be noted that a non-zero ground inductance Lg can be present. Such a non-zero ground inductance is not desirable as it will have a negative influence on the behaviour of the matching network.
FIG. 2A shows a basic representation of an inductor in an integrated circuit. In particular, the inductor has been placed in a two-port ground-signal-ground test configuration in order to test the performance of the IC inductor. In FIG. 2A, a representation of an IC inductor is depicted which can for example be used in the matching networks according to FIGS. 1a and 1b. It should be noted that the inductor performance evaluation structure according to FIG. 2A comprises two very wide ground lines GL placed symmetrically around the inductor I. It should further be noted that the ground lines GL need to be very wide to minimize the inductance Lg. Furthermore, they should be placed with sufficient clearance from the inductor to ensure that the performance of the inductor I is not affected. If the IC inductor according to FIG. 2A is investigated, for example by means of simulations, the result will correspond to the circuit of FIG. 1B instead of the circuit according to FIG. 1A. It should be noted that the huge area covered by the two ground lines can be a problem and is in particular not desirable. If the ground lines are removed or if their width is reduced, the ground inductance is increased significantly.
FIG. 2B shows an 8 shaped inductor according to the prior art. The inductor according to FIG. 2B corresponds to the inductor as depicted in WO 2004/012213 A1. If several conductors are placed adjacent to each other, a crosstalk between the inductors may lead to undesired effects. According to WO 2004/012213 A1, two oppositely directed current loops 211, 212 in an 8 shaped inductor are advantageous with respect to the cancellation of the magnetic fields such that the crosstalk can be reduced. The eye 209 of the winding to which the supply lines lead to is smaller than the other eye 210. This can be performed in order to compensate for the magnetic fields of the supply lines. The specific implementation of this requirement can be very tricky in particular as the geometry of the supply lines and the return path of the ground current should be known before the correction is performed.
FIG. 3 shows a three dimensional view of an inductor unit according to the prior art. Here, a ground path 200 and the inductor 100 is depicted. The inductor 100 comprises a number of turns 120 and is implemented as a planar inductor. The inductive component also comprises an underpass 110 which is used to couple one end of the inductor turns to one inductor terminal. It should be noted that the width as well as the clearance of the ground paths 200 have been reduced as compared to the inductor according to FIG. 2A. This is performed in order to minimize the footprint of the device.